The maximum integration density of modern integrated circuits (ICs) is limited by the amount of power or heat dissipated per unit area. In order to increase the device integration density, the power dissipation per device must be reduced steadily with time. An important method of reducing the device power consumption is to reduce the power supply voltage (VDD). Reducing VDD can decrease both the dynamic power consumption and the standby power consumption of future ICs. Device on-state current must be sufficiently large in order to achieve good circuit speed. Device off-current must be sufficiently small in order to suppress the standby power consumption. It is well known to those skilled in the art that the Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the device driving today's ICs, is limited in the ratio of on-state to off-state currents, ION/IOFF, when VDD is small. When VDD is small, a new transistor requiring smaller changes in the input voltage to effect a tenfold increase in the transistor current, a quantity called “swing” or “S” and measured in millivolts (mV)/decade, is highly desirable because the maximum change in the input voltage is normally equal to VDD. This requires an operating principle other than the passage of charge carriers over a potential barrier—the operating principle behind both MOSFETs and bipolar transistors. This operating principal behind both MOSFETs and bipolar transistors sets a floor of 60 mV/decade to the swing achievable at room temperature.
Various researchers have explored tunneling transistors. Tunneling transistors are transistors that operate based on a principle involving charge carriers tunneling under or passing through, rather than over, a potential barrier. Therefore, tunneling transistors are not subject to the 60 mV/decade limitation to swing. FIG. 1 illustrates a conventional tunneling transistor 10. In general, the conventional tunneling transistor 10 includes a substrate 12, an N+ source 14 and a P+ drain 16 formed in the substrate 12, and a gate stack 18 arranged as shown. The gate stack 18 may also be referred to as a gate. The gate stack 18 is generally formed of a metallic gate electrode 20 and a gate dielectric 22 arranged as shown. A p-type channel (a portion of the p-type substrate 12 between the N+ source 14 and the P+ drain 16) and the N+ source 14 form a gated PN diode. When this gated PN diode is reverse biased by applying a negative gate-to-source voltage (VGS), a tunneling current occurs at a vertical tunneling junction 24.
The conventional tunneling transistor 10 has at least two issues. First, best on-current (ION) reports for the conventional tunneling transistor 10 have been withdrawn. Remaining valid experiments have all shown that the on-current NO of the conventional tunneling transistor 10 is too low for general applications. Second, a large gate voltage is needed to turn on the conventional tunneling transistor 10. As such, there is a need for a new tunneling transistor having a suitable on-current (ION) for modern applications. There is also a need for a new tunneling transistor having a reduced turn-on voltage and is therefore capable of operating at lower supply voltage, or VDD, levels.